Storage device for processing merged transactions and method of operating the same

ABSTRACT

The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) toKorean patent application number 10-2020-0077968, filed on Jun. 25,2020, in the Korean Intellectual Property Office, the entire disclosureof which is incorporated herein by reference.

BACKGROUND 1. Field of Invention

The present disclosure relates to an electronic device, and moreparticularly, to a storage device and a method of operating the same.

2. Description of Related Art

A storage device is a device that stores data under control of a hostdevice, such as a computer or a smartphone. A storage device may includea memory device storing data and a memory controller controlling thememory device. The memory device may be classified as a volatile memorydevice or a non-volatile memory device.

The volatile memory device may be a device that stores data when poweris supplied and loses the stored data when the power supply is cut off.The volatile memory device may include a static random access memory(SRAM), a dynamic random access memory (DRAM), and so on.

The non-volatile memory device is a device that does not lose data whenpower is cut off. The non-volatile memory device may include a read onlymemory (ROM), a programmable ROM (PROM), an electrically programmableROM (EPROM), an electrically erasable and programmable ROM (EEPROM), aflash memory, and so on.

In the enterprise server market, due to increasing bandwidth demands andproblems of power consumption, a solid state disk (SSD) including a NANDflash memory, instead of a hard disk drive, is often utilized as astorage device.

Initial SSD controllers utilized an internal memory as a data buffer.However, recent SSD controllers use a DRAM as the data buffer, due tothe high speed demand. Most enterprise servers use a DRAM module, wherean expensive error correction code (ECC) function is applied as a mainmemory of a system bus to provide data stability for the servers.

SUMMARY

An embodiment of the present disclosure provides a storage device havingan improved operation speed, and a method of operating the same.

A volatile memory controller that controls a volatile memory deviceaccording to an embodiment of the present disclosure may include anerror correction circuit configured to receive write transactions froman external host, wherein the write transactions store data in thevolatile memory device and generate codewords used when performing errorcorrection encoding on data corresponding to the write transactions anda data aggregator configured to generate a merged transaction in whichwrite transactions that correspond to a burst length of the volatilememory device are merged and provide the merged transaction to thevolatile memory device by performing a burst operation.

A storage device according to an embodiment of the present disclosuremay include a nonvolatile memory device a main memory configured totemporarily store data related to controlling the nonvolatile memorydevice and a memory controller configured to control the nonvolatilememory device and the main memory under control of an external host,wherein the main memory aggregates and processes a number of writetransactions having continuous addresses, among write transactionsreceived from the memory controller, equal to a burst length unit of themain memory.

According to the present technology, a storage device having an improvedoperation speed, and a method of operating the same are provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a storage device according to an embodiment of thepresent disclosure.

FIG. 2 illustrates a memory device of FIG. 1.

FIG. 3 illustrates a configuration of any one of the memory blocks ofFIG. 2.

FIG. 4 illustrates an error correction encoding operation performed whendata is stored in a main memory device.

FIG. 5 illustrates an address mapping method for storing parity data.

FIG. 6 illustrates an operation of a main memory according to anembodiment of the present disclosure.

FIG. 7 illustrates an operation of the storage device according to anembodiment of the present disclosure.

FIG. 8 illustrates an operation of a scheduler and an internal bufferdescribed with reference to FIG. 7.

FIG. 9 illustrates an operation of a data aggregator when a mergedtransaction is not generated.

FIG. 10 illustrates an operation of a main memory included in thestorage device according to an embodiment of the present disclosure.

FIG. 11 illustrates another embodiment of the memory controller of FIG.1.

FIG. 12 illustrates a memory card system where the storage deviceaccording to an embodiment of the present disclosure is applied.

FIG. 13 illustrates a solid state drive (SSD) system where the storagedevice according to an embodiment of the present disclosure is applied.

FIG. 14 illustrates a user system where the storage device according toan embodiment of the present disclosure is applied.

DETAILED DESCRIPTION

Specific structural or functional descriptions of embodiments accordingto the concept which are disclosed in the present specification orapplication are illustrated only to describe the embodiments accordingto the concept of the present disclosure. The embodiments according tothe concept of the present disclosure may be carried out in variousforms and the descriptions are not limited to the embodiments describedin the present specification or application.

FIG. 1 illustrates a storage device according to an embodiment of thepresent disclosure.

Referring to FIG. 1, the storage device 50 may include a memory device100 and a memory controller 200 that controls an operation of the memorydevice 100. The storage device 50 may be a device that stores data undercontrol of a host 400, such as a cellular phone, a smartphone or othermobile device, an MP3 player, a laptop computer, a desktop computer, agame player or gaming system, a TV, a tablet PC, an in-vehicleinfotainment system, and so on.

The storage device 50 may be manufactured as one of various types ofstorage devices that communicate with the host 400 via a host interface.For example, the storage device 50 may be configured as any one ofvarious types of storage devices, such as an SSD, a multimedia card in aform of a MMC (MultiMediaCard), an eMMC (embedded MMC), an RS-MMC(Reduced Size MMC) and a micro-MMC, a secure digital card in a form ofan SD, a mini-SD and/or a micro-SD, a universal serial bus (USB) storagedevice, a universal flash storage (UFS) device, a personal computermemory card international association (PCMCIA) card type storage device,a peripheral component interconnection (PCI) card type storage device, aPCI express (PCI-E) card type storage device, a compact flash (CF) card,a smart media card, and a memory stick.

The storage device 50 may be manufactured as any one of various types ofpackages. For example, the storage device 50 may be manufactured as anyone of various types of package types, such as a package on package(POP), a system in package (SIP), a system on chip (SOC), a multi-chippackage (MCP), a chip on board (COB), a wafer-level fabricated package(WFP), and a wafer-level stack package (WSP).

The memory device 100 may store data. The memory device 100 operatesunder control of the memory controller 200. The memory device 100 mayinclude a memory cell array (not shown) including a plurality of memorycells that store data.

Each of the memory cells may be configured as a single level cell (SLC)that stores one data bit, a multi-level cell (MLC) that stores two databits, a triple level cell (TLC) that stores three data bits, or a quadlevel cell (QLC) capable of storing four data bits.

The memory cell array (not shown) may include a plurality of memoryblocks. One memory block may include a plurality of pages. In anembodiment, the page may be a unit for storing data in the memory device100 or reading data stored in the memory device 100. The memory blockmay be a unit for erasing data.

In an embodiment, the memory device 100 may be a double data ratesynchronous dynamic random access memory (DDR SDRAM), a low power doubledata rate4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, alow power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), aNAND flash memory, a vertical NAND flash memory, a NOR flash memorydevice, a resistive random access memory (RRAM), a phase-change memory(PRAM), a magnetoresistive random access memory (MRAM), a ferroelectricrandom access memory (FRAM), a spin transfer torque random access memory(STT-RAM), and so on. In the present specification, for convenience ofdescription, the memory device 100 may be a NAND flash memory.

The memory device 100 is configured to receive a command CMD and anaddress ADDR from the memory controller 200 and access an area selectedby an address in the memory cell array. The memory device 100 mayperform an operation instructed by the command CMD on the areaidentified or referenced by the address ADDR. For example, the memorydevice 100 may perform a write operation (e.g., a program operation), aread operation, and/or an erase operation. During the program operation,the memory device 100 may program data in the area identified by theaddress ADDR. During the read operation, the memory device 100 may readdata from the area identified by the address ADDR. During the eraseoperation, the memory device 100 may erase data stored in the areaidentified by the address ADDR.

The memory controller 200 may control an overall operation of thestorage device 50. In an embodiment, the memory controller 200 is adigital circuit that manages the flow of data going to and from thememory device 100. The memory controller 200 may be formed on a chipindependently or integrated with one or more other circuits.

When power is applied to the storage device 50, the memory controller200 may execute firmware (FW). When the memory device 100 is a flashmemory device, the firmware (FW) may include a host interface layer(HIL) that controls communication with the host 400, a flash translationlayer (FTL) that controls communication between the memory controller200 and the host 400, and a flash interface layer (FIL) that controlscommunication with the memory device 100.

In an embodiment, the memory controller 200 may receive data and alogical block address (LBA) from the host 400 and may convert the LBAinto a physical block address (PBA), which indicates an address ofmemory cells in which data included in the memory device 100 is to bestored. In the present specification, the LBA and a “logic address” or a“logical address” may be used interchangeably. In the presentspecification, the PBA and a “physical address” may be usedinterchangeably.

The memory controller 200 may control the memory device 100 to performthe program operation, the read operation, and/or the erase operationaccording to a request provided by the host 400. During the programoperation, the memory controller 200 may provide a write command, thePBA, and data to the memory device 100. During the read operation, thememory controller 200 may provide a read command and the PBA to thememory device 100. During the erase operation, the memory controller 200may provide an erase command and the PBA to the memory device 100.

In an embodiment, the memory controller 200 may generate a command, anaddress, and data independently or without receiving a request from thehost 400. The memory controller 200 may transmit the command, theaddress, and/or the data to the memory device 100. For example, thememory controller 200 may provide a command, an address, and/or data forperforming a read operation and associated program, such as wearleveling, read reclaim, garbage collection, and so on, to the memorydevice 100.

In an embodiment, the memory controller 200 may control at least two ormore memory devices 100. In this case, the memory controller 200 maycontrol the memory devices 100 according to an interleaving method toimprove operation performance. The interleaving method may be a methodof controlling operations for at least two memory devices 100, where theperformance of the operations overlap with each other.

The main memory 300 may temporarily store data received from the host400 or may temporarily store data received from the memory device 100.The main memory 300 may operate under control of the host 400. In anembodiment, the main memory 300 may be a volatile memory device. Forexample, the main memory 300 may be a dynamic random access memory(DRAM) or a static random access memory (SRAM).

The main memory 300 may provide data to the memory device 100 accordingto a request provided by or received from the memory controller 200, ormay provide data to the host 400. In an embodiment, the main memory 300may provide data to the memory controller 200 and/or store data receivedfrom the memory controller 200.

The main memory 300 may perform an encoding operation and/or a decodingoperation using an error correction code to detect or correct an errorbit included in the stored data.

In an embodiment, the memory controller 200 may read metadata stored inthe memory device 100 and store the read metadata in the main memory300.

The metadata may be data including various information required or usedto control the storage device 50. For example, the metadata may includebad block information, which is information on a bad block or bad blocksamong a plurality of memory blocks included in the memory device 100,and firmware to be executed by a processor 210 of the memory controller200.

In an embodiment, the metadata may include map data, which indicates orcontains a correspondence or relationship between the logical addressprovided by the host 400 and the physical address of the memory cellsincluded in the memory device 100. Further, the metadata may include avalid page table, which indicates whether data stored in pages includedin the memory device 100 is valid data. In an embodiment, the valid pagetable data may include a plurality of valid page tables. The valid pagetable may be data of a bitmap form indicating whether data stored in apage in a 4 KB unit is valid.

Alternatively, in various embodiments, the metadata may include readcount data indicating the number of instances of read operationsperformed on the memory blocks included in the memory device 100,cycling data indicating the number of instances of erasures of thememory blocks included in the memory device 100, hot/cold dataindicating whether the data stored in the pages included in the memorydevice 100 is hot data or cold data, and/or journal data indicatingchanges to the contents of the map data.

In an embodiment, the metadata stored in the main memory 300 may includedata chunks having different types of data structures for each type. Forexample, the metadata may have different data sizes for each type.Therefore, the size of the metadata stored in the main memory 300 may bedifferent for each type.

In an embodiment of the present disclosure, the memory controller 200may include the processor 210 and a cache memory 220.

The processor 210 may control an overall operation of the memorycontroller 200. The processor 210 may control the main memory 300 toread the data stored in the main memory 300, change the data, and thenstore the data back in the main memory 300.

The processor 210 may execute firmware (FW). The processor 210 mayperform operations required or used to access the memory device 100. Forexample, the processor 210 may provide a command to the memory device100 and control the memory device 100 and the main memory 300 to performan operation corresponding to or based on the command.

For example, when a write request is received from the host 400, theprocessor 210 may convert a logical address corresponding to the writerequest into a physical address. The processor 210 may store the mapdata, which is the correspondence or relationship between the logicaladdress and the physical address, in the main memory 300.

In order to store the map data, the processor 210 may read a map segmentthat includes mapping information of the logical address provided by thehost 400 from the main memory 300. Thereafter, the processor 210 mayrecord the physical address corresponding to the logical address in themap segment. The processor 210 may store the map segment that recordedthe physical address back in the main memory 300. When the physicaladdress is allocated, the data of the valid page table corresponding toan associated physical address may also be updated.

In an embodiment, the map data stored in the main memory 300 may beupdated. For example, when a write request of new data is input withrespect to a previously write requested logical address, previouslystored data may become invalid data, and a physical addresscorresponding to the logical address may be changed. Alternatively, whenstored data is changed by various background operations, such as garbagecollection, read reclaim, and/or wear leveling, the map data may beupdated.

The cache memory 220 may store data accessed by the processor 210 fromthe main memory 300. A capacity of the cache memory 220 may be smallerthan that of the main memory 300. In an embodiment, the cache memory 220may be a volatile memory device. For example, the main memory 300 may bea dynamic random access memory (DRAM) or a static random access memory(SRAM). The cache memory 220 may be a memory having an operation speedfaster than that of the main memory 300.

Because the capacity of the cache memory 220 is smaller than that of themain memory 300, the cache memory 220 may store only metadata accessedby the processor 210, with respect to all the metadata stored in themain memory 300. The storing of data associated with a specific address,with respect to all the data stored in the main memory 300, in the cachememory 220 is referred to as caching.

When the cache memory 220 stores data to be accessed by the processor210 from the main memory 300, the cache memory 220 may provide the datato the processor 210. Since the operation speed of the cache memory 220is faster than that of the main memory 300, when the data to be accessedby the processor 210 is stored in the cache memory 220, the processor210 may obtain the data faster than instead obtaining the data from themain memory 300.

A cache hit occurs when data to be accessed by the processor 210 isstored in the cache memory 220, and a cache miss occurs when data to beaccessed by the processor 210 is not stored in the cache memory 220.When cache hits increase for the cache memory 220, the speed of anoperation processed by the processor 210 may also increase.

A method of operating the cache memory 220 may be classified or called adirect mapped cache, a set associative cache, and/or a fully associativecache.

The direct mapped cache method of operation may be a method in which aplurality of addresses of the main memory 300 operate in a many-to-one(n:1) method corresponding to one address of the cache memory 220. Thatis, the direct mapped cache method of operation may be an operationmethod having an address of the cache memory (not shown) in which datathat is stored in a specific address of the main memory 300 may becached is mapped and fixed in advance.

The fully associative cache may be a method of operation in which theaddress of the cache memory (not shown) and the address of the mainmemory 300 are not fixedly mapped and the address of an empty cachememory (not shown) may cache data stored in any address of the mainmemory 300. The fully associative cache is required or used to searchall addresses when determining the occurrence of a cache hit or cachemiss.

The set associative cache method of operation is an intermediate form ofthe direct mapped cache and the fully associative cache, and manages thecache memory (not shown) by dividing the cache memory (not shown) into aplurality of cache sets. The cache set may be divided into cache ways ora cache line that are also managed.

The host 400 may communicate with the storage device 50 using at leastone of various communication methods or protocols, such as a universalserial bus (USB), a serial AT attachment (SATA), a serial attached SCSI(SAS), a high speed interchip (HSIC), a small computer system interface(SCSI), a peripheral component interconnection (PCI), a PCI express(PCIe), a nonvolatile memory express (NVMe), a universal flash storage(UFS), a secure digital (SD), a multi-media card (MMC), an embedded MMC(eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM),and/or a load reduced DIMM (LRDIMM).

FIG. 2 illustrates the memory device 100 of FIG. 1.

Referring to FIG. 2, the memory device 100 may include a memory cellarray 110, a voltage generator 120, an address decoder 130, aninput/output circuit 140, and a control logic 150.

The memory cell array 110 includes a plurality of memory blocks BLK1 toBLKi. The plurality of memory blocks BLK1 to BLKi are connected to theaddress decoder 130 through row lines RL. The plurality of memory blocksBLK1 to BLKi may be connected to the input/output circuit 140 throughcolumn lines CL. In an embodiment, the row lines RL may include wordlines, source select lines, and drain select lines. In an embodiment,the column lines CL may include bit lines.

Each of the plurality of memory blocks BLK1 to BLKi includes a pluralityof memory cells. In an embodiment, the plurality of memory cells may benon-volatile memory cells. Memory cells connected to the same word lineamong the plurality of memory cells may be defined as one physical page.That is, the memory cell array 110 may include a plurality of physicalpages. Each of the memory cells of the memory device 100 may beconfigured as a single level cell (SLC) that stores one data bit, amulti-level cell (MLC) that stores two data bits, a triple level cell(TLC) that stores three data bits, or a quad level cell (QLC) capable ofstoring four data bits.

In an embodiment, the voltage generator 120, the address decoder 130,and the input/output circuit 140 may be collectively referred to as aperipheral circuit. The peripheral circuit may drive the memory cellarray 110 under control of the control logic 150. The peripheral circuitmay drive the memory cell array 110 to perform the program operation,the read operation, and/or the erase operation.

The voltage generator 120 is configured to generate a plurality ofoperation voltages Vop using an external power voltage supplied to thememory device 100. The voltage generator 120 operates in response to thecontrol of the control logic 150.

As an embodiment, the voltage generator 120 may generate an internalpower voltage by regulating the external power voltage. The internalpower voltage generated by the voltage generator 120 is used as anoperation voltage of the memory device 100.

As an embodiment, the voltage generator 120 may generate the pluralityof operation voltages using an external power voltage or an internalpower voltage. The voltage generator 120 may be configured to generatevarious voltages required in the memory device 100. For example, thevoltage generator 120 may generate a plurality of erase voltages, aplurality of program voltages, a plurality of pass voltages, a pluralityof selected read voltages, and/or a plurality of unselected readvoltages.

The voltage generator 120 may include a plurality of pumping capacitorsthat receive the internal power voltage to generate the plurality ofoperation voltages having various voltage levels and may generate theplurality of operation voltages by selectively activating the pluralityof pumping capacitors in response to the control of the control logic150.

The generated plurality of operation voltages may be supplied to thememory cell array 110 by the address decoder 130.

The address decoder 130 is connected to the memory cell array 110through the row lines RL. The address decoder 130 is configured tooperate in response to the control of the control logic 150. The addressdecoder 130 may receive an address or addresses ADDR from the controllogic 150. The address decoder 130 may decode a block address among thereceived addresses ADDR. The address decoder 130 selects at least onememory block of the memory blocks BLK1 to BLKi according to or based onthe decoded block address. The address decoder 130 may decode a rowaddress from the received addresses ADDR. The address decoder 130 mayselect at least one word line among the word lines of a selected memoryblock according to or based on the decoded row address. In anembodiment, the address decoder 130 may decode a column address from thereceived addresses ADDR. The address decoder 130 may connect theinput/output circuit 140 and the memory cell array 110 to each otheraccording to or based on the decoded column address.

For example, the address decoder 130 may include components such as arow decoder, a column decoder, and an address buffer.

The input/output circuit 140 may include a plurality of page buffers.The plurality of page buffers may be connected to the memory cell array110 through the bit lines. During the program operation, data may bestored in selected memory cells according to data stored in theplurality of page buffers.

During the read operation, the data stored in the selected memory cellsmay be sensed through the bit lines, and the sensed data may be storedin the page buffers.

The control logic 150 may control the address decoder 130, the voltagegenerator 120, and the input/output circuit 140. The control logic 150may operate in response to the command CMD received from and/ortransmitted by an external device. The control logic 150 may generatevarious signals in response to the command CMD and the address ADDR tocontrol the peripheral circuits.

FIG. 3 illustrates a configuration of any one of the memory blocks ofFIG. 2.

The memory block BLKi is any one BLKi of the memory blocks BLK1 to BLKiof FIG. 2.

Referring to FIG. 3, a plurality of word lines arranged in parallel witheach other may be connected between a first select line and a secondselect line. As shown, the first select line may be the source selectline SSL, and the second select line may be the drain select line DSL.More specifically, the memory block may include a plurality of stringsST connected between the bit lines BL1 to BLn and the source line SL.The bit lines BL1 to BLn may be connected to the strings ST,respectively, and the source line SL may be connected to the strings ST.Because the strings ST may be configured to be identical to each other,a string ST connected to the first bit line BL1 will now be specificallydescribed, as an example.

The string ST may include a source select transistor SST, a plurality ofmemory cells MC1 to MC16, and a drain select transistor DST connected inseries between the source line SL and the first bit line BL1. One stringST may include at least one or more of the source select transistor SSTand the drain select transistor DST, and may include the memory cellsMC1 to MC16, and/or additional memory cells not shown in the figure.

A source of the source select transistor SST may be connected to thesource line SL and a drain of the drain select transistor DST may beconnected to the first bit line BL1. The memory cells MC1 to MC16 may beconnected in series between the source select transistor SST and thedrain select transistor DST. Gates of the source select transistors SSTincluded in the different strings ST may be connected to the sourceselect line SSL, gates of the drain select transistors DST may beconnected to the drain select line DSL, and gates of the memory cellsMC1 to MC16 may be connected to the plurality of word lines WL1 to WL16.A group of the memory cells connected to the same word line among thememory cells included in different strings ST may be referred to as apage PG. Therefore, the memory block BLKi may include pages PG equal tothe number of the word lines WL1 to WL16.

One memory cell may store one bit of data. This is generally called asingle level cell (SLC). In this case, one physical page PG may storeone logical page (LPG) data. The one logical page (LPG) data may includedata bits equal in number as the cells included in one physical page PG.

The one memory cell may store two or more bits of data. In this case,one physical page PG may store two or more logical page (LPG) data.

FIG. 4 illustrates an error correction encoding operation performed whendata is stored in a main memory device.

Referring to FIG. 4, the main memory may receive data to be stored fromthe memory device 100, the memory controller 200, and/or the host 400,as described with reference to FIG. 1. The data to be stored in the mainmemory may be write data requested by the host 400 to be stored in thememory device 100, read data read from the memory device 100, and/ordata requested by the memory controller 200 to be stored in the mainmemory.

The data received by the main memory may be message data (Message Data).In an embodiment, the message data (Message Data) may have a size of 32bytes.

The main memory may include its own error correction code engine (ECCengine) for detection and correction of an error bit of the data to bestored. In an embodiment, an error correction code used by the ECCengine may be BCH (Bose-Chaudhuri-Hocquenghem), Reed Solomon, Hammingcode, low density parity check code (LDPC), redundant array ofindependent disks (RAID), cyclic redundancy check (CRC), and so on.

The ECC engine may encode the message data (Message Data) using theerror correction code. A codeword may be generated as a result of theencoding operation on the message data (Message Data). The codeword mayinclude the message data (Message Data) and parity data (Parity Data).The main memory may store the codeword in a main memory device (MainMemory Device).

In order to store the parity data (Parity Data) in the main memorydevice, the main memory may use an address mapping method, includingseparate mode mapping and/or continuous mode mapping.

FIG. 5 illustrates describing the address mapping methods for storingthe parity data.

Referring to FIG. 5, the main memory may use the separate mode mappingor the continuous mode mapping methods to store the parity data (ParityData) in the main memory device.

The separate mode mapping may be a mapping method in which message dataand the parity data have different base addresses.

A first mapping table 501 may include mapping information containingaddresses, to which the message data and the parity data are to bestored, are allocated according to the separate mode mapping. Accordingto the separate mode mapping method, an additional transaction thatperforms a separate write or read operation may be required or utilizedto store or read the parity data. Further, a transaction may be anaccess unit that stores data in the main memory or reads data from themain memory.

The continuous mode mapping may be a mapping method in which the messagedata and the parity data have the same base address or continuousaddresses.

A second mapping table 503 may include mapping information containing anaddress, in which the message data and the parity data are to be stored,is allocated according to the continuous mode mapping. According to thecontinuous mode mapping method, the message data and the parity data mayhave the same base address and may be accessed by one transaction.Alternatively, because the message data and the parity data have thecontinuous addresses, the message data and the parity data may beprocessed together using a burst operation. Therefore, an additionaltransaction for access of the parity data may not occur or be performed.

Therefore, storing the parity data according to the continuous modemapping method instead of the separate mode mapping method does not useor require an additional transaction. Thus, storing the parity datausing the continuous mode mapping method may increase the operationalefficiency of a memory.

However, in a case of the continuous mode mapping method, because theparity data is transmitted immediately after the message data, addressalignment may be broken. Although the method performs a singlecontinuous transaction, the single continuous transaction may beprocessed as separate internal transactions, a transaction for themessage data and a transaction for the parity data.

Therefore, when the ECC engine is used, the continuous mode mappingmethod may be more efficient than the separate mode mapping method, butthe efficiency may be reduced when the ECC engine is not used.

In an embodiment of the present disclosure, when the ECC engine is used,a data aggregator is provided to improve a memory efficiency reduction,and a method of improving the memory efficiency reduction is performed.

FIG. 6 illustrates an operation of the main memory according to anembodiment of the present disclosure.

Referring to FIG. 6, the main memory 300 may include an operationcontroller 310 and a main memory device 320. In an embodiment, theoperation controller 310 may be a DRAM controller (volatile memorycontroller), and the main memory device 320 may be a DRAM (volatilememory device).

The operation controller 310 may include an ECC engine 311 and a dataaggregator 312.

The ECC engine 311 may receive data to be stored in the main memorydevice 320 from the memory device 100, the memory controller 200, and/orthe host 400, as described with reference to FIG. 1. In an embodiment,the data to be stored in the main memory device 320 may include writedata requested by the host 400 to be stored in the memory device 100,read data read from the memory device 100, and/or data requested by thememory controller 200 to be stored in the main memory.

The ECC engine 311 may encode the received data using the errorcorrection code. The error correction code used by the ECC engine 311may be BCH, Reed Solomon, Hamming code, low density parity check code(LDPC), redundant array of independent disks (RAID), cyclic redundancycheck (CRC), and so on

The ECC engine 311 may provide the codeword to the data aggregator 312.

The data aggregator 312 may receive the codeword from the ECC engine311. The data aggregator 312 may provide a write completion response tothe ECC engine in response to the received codeword. The write completeresponse may be a response indicating that the codeword is successfullystored in the main memory device 320. The ECC engine 311 may provide thereceived write completion response to the memory device 100, the memorycontroller 200, and/or the host 400 that provides the data to be stored.

The main memory device 320 may perform the burst operation, as describedherein. Here, the burst operation refers to an operation in which themain memory device 320 writes or reads a large amount of data bysequentially decreasing or increasing an address from an initial addressreceived from the data aggregator 312. A basic unit of the burstoperation is referred to as a burst length (BL). In an embodiment, theBL may be the number of continuous read or write operations byincreasing or decreasing the address from the initial address. Forexample, in a case where the main memory device 320 is a double datarate (DDR) DRAM, when the BL is 8 (BL=8), the burst read operation orwrite operation is performed eight times continuously from the initialaddress in response to a clock (CLK).

The BL may be determined by a user. That is, the data aggregator 312 mayset the BL under control of the host 400. Further, the main memory 300may further include a global register (not shown) that storesinformation on or about the BL. In an embodiment, the main memory device320 may include a plurality of storage areas. For example, the mainmemory device 320 may include a plurality of banks. In this case, the BLmay be set differently or uniquely for each of the plurality of storageareas.

In an embodiment, the data aggregator 312 may temporarily store thereceived codewords without providing the codewords to the main memorydevice 320 until a predetermined size is reached. Alternatively, thedata aggregator 312 may temporarily store the received codewords withoutproviding the codewords to the main memory device 320 until apredetermined number of write transactions are collected. In anembodiment, the predetermined size may be a data size corresponding tothe BL of the main memory device 320. Alternatively, the predeterminednumber of write transactions may be the BL.

FIG. 7 illustrates an operation of the storage device according to anembodiment of the present disclosure.

Referring to FIG. 7, the memory controller 200 may provide the data,which is to be stored in the main memory device 320, to the operationcontroller 310.

The operation controller 310 may include the ECC engine 311 and the dataaggregator 312.

The data aggregator 312 may include a scheduler 312-1, an internalbuffer 312-2, and an aggregation controller 312-3.

The ECC engine 311 may generate the codeword obtained by encoding thedata to be stored using the error correction code, as described herein.In an embodiment, the codeword may include the message data (e.g.,original data), and the parity data corresponding to the errorcorrection code. The ECC engine 311 may provide the codeword to the dataaggregator 312.

The data aggregator 312 may control the main memory device 320 toperform a write operation of storing data in the main memory device 320or a read operation of reading data from the main memory device 320. Themain memory device 320 may operate using transactions. That is, the dataaggregator 312 may provide a write transaction (e.g., a request toperform a write operation) or a read transaction (e.g., a request toperform a read operation) to the main memory device 320.

The scheduler 312-1 may operate in response to control of theaggregation controller 312-3. For example, the write transactionprovided from the ECC engine 311 may be stored in a provided sequenceunder control of the scheduler 312-1.

The internal buffer 312-2 may store the codeword corresponding to thewrite transaction under the control of the aggregation controller 312-3.

The aggregation controller 312-3 may receive the codeword from the ECCengine 311. The aggregation controller 312-3 may store the codeword inthe internal buffer 312-2 and provide a write completion response to theECC engine 311. The aggregation controller 312-3 may store the writetransaction in the scheduler 312-1. The write transaction may includeinformation on a write address corresponding to the codeword to bestored.

When the codewords stored in the internal buffer 312-2 reach apredetermined size, the aggregation controller 312-3 may generate amerged transaction, in which the write transactions corresponding to orassociated with the stored codewords are merged, and provide thegenerated merged transaction to the main memory device 320.

Alternatively, when the predetermined number of write transactions arestored in the scheduler 312-1, the aggregation controller 312-3 maygenerate the merged transaction, in which the stored write transactionsare merged, and provide the generated merged transaction to the mainmemory device 320. Addresses corresponding to the write transactionsincluded in the merged transaction may be continuous addresses. In anembodiment, the predetermined size may be a data size corresponding tothe burst length of the main memory device 320. Alternatively, thepredetermined number of write transactions may be the burst length.

FIG. 8 illustrates an operation of the scheduler and the internal bufferdescribed with reference to FIG. 7.

Referring to FIGS. 7 and 8, the scheduler 312-1 may store the inputwrite transaction according to or based on an input sequence. In FIG. 8,the burst length is assumed or pre-selected to be four.

In FIG. 8, the scheduler 312-1 stores first to eighth write transactions(e.g., TRSAC). The internal buffer 312-2 may store a first codewordCODEWORD1 to an eighth codeword CODEWORD8, which correspond to a firstwrite transaction to an eighth write transaction.

A first merged transaction (Merged Transaction1) may include the firstto fourth write transactions. A second merged transaction (MergedTransaction2) may include the fifth to eighth write transactions.

Write transactions that may be merged into a merged transaction may havecontinuous addresses. For example, the first to fourth writetransactions have continuous addresses, first address ADDR1 to fourthaddress ADDR4, respectively, and the fifth to eighth write transactionshave continuous addresses, fifth address ADDR5 to eighth address ADDR8,respectively.

Since the burst length of the merged transaction is four, the mergedtransaction may be generated when four write transactions are stored inthe scheduler 312-1. Alternatively, the merged transaction may receivewrite transactions for a predetermined time, and then may be generatedin a lump.

Because all of the first to eighth write transactions in FIG. 8 arewrite transactions in which addresses are continuous, a mergedtransaction that merges any four write transactions may be generated,including merged transactions not shown in FIG. 8. For example, a mergedtransaction may include the first write transaction, the third writetransaction, the fourth write transaction, and the seventh writetransaction.

The aggregation controller 312-3 described with reference to FIG. 7 mayprovide the merged transaction to the main memory device 320 accordingto the burst operation.

FIG. 9 illustrates an operation of the data aggregator when a mergedtransaction is not generated.

Referring to FIG. 9, the aggregation controller 312-3 may control thescheduler 312-1 and the internal buffer 312-2 to perform a flushoperation of providing the write transaction stored in the scheduler312-1 to the main memory device 320 without generating a mergedtransaction.

For example, the aggregation controller 312-3 may control the scheduler312-1 and the internal buffer 312-2 to perform the flush operation inresponse to an event signal generated in the main memory 300. Here, theevent signal may be generated when the continuity of the addresses ofthe write transactions is broken, a read transaction for the sameaddress as the address of the write transaction stored in the scheduler312-1 is received, and/or a forced flush request is received from thememory controller 200. In an embodiment, the forced flush request may beinput when an emergency situation occurs, such as a sleep mode thatreduces power consumption of the storage device 50 or a sudden power ofthe storage device 50 off occurs.

Specifically, when the addresses of the write transactions stored in thescheduler 312-1 are not continuous (e.g., the continuity of theaddresses of the write transactions is broken), the aggregationcontroller 312-3 may provide each write transaction to the main memorydevice 320 without generating a merged transaction. For example, when awrite transaction having an address that is not continuous with theaddress of the write transactions stored in the scheduler 312-1 isprovided, the aggregation controller 312-3 may provide each writetransaction to the main memory device 320 without generating a mergedtransaction.

Alternatively, before generating the merged transaction, when theaddress for the read transaction is the same address as the address ofthe write transaction stored in the scheduler 312-1 is received, inorder to avoid a data hazard, the aggregation controller 312-3 mayprovide each write transaction to the main memory device 320 withoutgenerating a merged transaction. The aggregation controller 312-3 mayprovide a read transaction to the main memory device 320 aftercompletion of the write transaction.

Alternatively, the aggregation controller 312-3 may provide each writetransaction to the main memory device 320 without generating a mergedtransaction in response to the forced flush input, which is input fromthe outside of the device.

In an embodiment, when the write transactions corresponding to the burstlength are stored in the scheduler 312-1, the aggregation controller312-3 may generate a merged transaction, provide the merged transactionto the main memory device 320, and then store newly input writetransactions in the scheduler 312-1.

FIG. 10 illustrates an operation of a main memory included in thestorage device according to an embodiment of the present disclosure.

Referring to FIG. 10, in step S1001, the main memory may receive thewrite transaction. The write transaction may be input from any one ofthe memory controller 200, the memory device 100, and/or the host 400,as described with reference to FIG. 1.

In step S1003, the main memory may perform error correction encoding onthe write data, which is data corresponding to or associated with thewrite transaction.

In step S1005, the main memory may first provide the write completionresponse to the memory controller 200 that provides the writetransaction.

In step S1007, the main memory stores the codeword, which is encodeddata, in the internal buffer.

In step S1009, the main memory may determine whether the writetransactions corresponding to the burst length are stored in theinternal buffer. When the write transactions corresponding to the burstlength are not stored, the operation returns to step S1001. When thewrite transactions corresponding to the burst length are stored, theoperation proceeds to Step S1011.

In step S1011, the main memory may generate the merged transaction, inwhich the write transactions are merged, and provide the mergedtransaction to the main memory to store data in the main memory device.Here, the write transactions included in the merged transaction may bethe write transactions with the continuous addresses.

FIG. 11 illustrates another embodiment of the memory controller of FIG.1.

Referring to FIGS. 1 and 11, the memory controller 1200 may include aprocessor 1210, a RAM 1220, an error correction circuit 1230, a ROM1260, a host interface 1270, and a flash interface 1280.

The processor 1210 may control overall operations of the memorycontroller 1200. The RAM 1220 may be used as a buffer memory, a cachememory, and an operation memory of the memory controller 1200. Forexample, the cache memory 220, described with reference to FIG. 1, maybe the RAM 1220, and may be an SRAM in an embodiment.

The ROM 1260 may store various information required for the memorycontroller 1200 to operate in a firmware form.

The memory controller 1200 may communicate with an external device (forexample, the host 400, an application processor, and the like) throughthe host interface 1270.

The memory controller 1200 may communicate with the memory device 100through the flash interface 1280. The memory controller 1200 maytransmit a command CMD, an address ADDR, and a control signal CTRL tothe memory device 100 through the flash interface 1280 and receive dataDATA. For example, the flash interface 1280 may include a NANDinterface.

FIG. 12 illustrates a memory card system to which the storage deviceaccording to an embodiment of the present disclosure is applied.

Referring to FIG. 12, the memory card system 2000 includes a memorycontroller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 is connected to the memory device 2200. Thememory controller 2100 is configured to access the memory device 2200.For example, the memory controller 2100 may be configured to controlread, write, erase, and background operations of the memory device 2200.The memory controller 2100 is configured to provide an interface betweenthe memory device 2200 and a host. The memory controller 2100 isconfigured to drive firmware for controlling the memory device 2200. Thememory controller 2100 may be implemented as the memory controller 200described with reference to FIG. 1.

For example, the memory controller 2100 may include components such as arandom access memory (RAM), a processor, a host interface, a memoryinterface, and an error corrector.

The memory controller 2100 may communicate with an external devicethrough the connector 2300. The memory controller 2100 may communicatewith an external device (e.g., the host) according to a specificcommunication standard or protocol. For example, the memory controller2100 is configured to communicate with an external device through atleast one of various communication standards such as a universal serialbus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheralcomponent interconnection (PCI), a PCI express (PCI-E), an advancedtechnology attachment (ATA), a serial-ATA, a parallel-ATA, a smallcomputer system interface (SCSI), an enhanced small disk interface(ESDI), integrated drive electronics (IDE), FireWire, a universal flashstorage (UFS), Wi-Fi, Bluetooth, and an NVMe. For example, the connector2300 may be defined by at least one of the various communicationstandards described above.

For example, the memory device 2200 may be configured of variousnon-volatile memory elements, such as an electrically erasable andprogrammable ROM (EEPROM), a NAND flash memory, a NOR flash memory, aphase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM(FRAM), and a spin-transfer-torque magnetic RAM (STT-MRAM).

The memory controller 2100 and the memory device 2200 may be integratedinto one semiconductor device to configure a memory card. For example,the memory controller 2100 and the memory device 2200 may be integratedinto one semiconductor device to configure a memory card such as a PCcard (personal computer memory card international association (PCMCIA)),a compact flash (CF) card, a smart media card (SM or SMC), a memorystick, a multimedia card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card(SD, miniSD, microSD, or SDHC), and a universal flash storage (UFS).

FIG. 13 illustrates a solid state drive (SSD) system to which thestorage device according to an embodiment of the present disclosure isapplied.

Referring to FIG. 13, the SSD system 3000 includes a host 3100 and anSSD 3200. The SSD 3200 exchanges a signal SIG with the host 3100 througha signal connector 3001 and receives power PWR through a power connector3002. The SSD 3200 includes an SSD controller 3210, a plurality of flashmemories 3221 to 322 n, an auxiliary power supply 3230, and a buffermemory 3240.

According to an embodiment of the present disclosure, the SSD controller3210 may perform the function of the memory controller 200, as describedwith reference to FIG. 1.

The SSD controller 3210 may control the plurality of flash memories 3221to 322 n in response to the signal SIG received from the host 3100. Forexample, the signal SIG may be signals based on an interface between thehost 3100 and the SSD 3200. For example, the signal SIG may be a signaldefined by at least one of interfaces such as a universal serial bus(USB), a multimedia card (MMC), an embedded MMC ((eMMC), a peripheralcomponent interconnection (PCI), a PCI express (PCI-E), an advancedtechnology attachment (ATA), a serial-ATA, a parallel-ATA, a smallcomputer system interface (SCSI), an enhanced small disk interface(ESDI), integrated drive electronics (IDE), FireWire, a universal flashstorage (UFS), Wi-Fi, Bluetooth, and an NVMe.

The auxiliary power supply 3230 is connected to the host 3100 throughthe power connector 3002. The auxiliary power supply 3230 may receivethe power PWR from the host 3100 and may charge the power. The auxiliarypower supply 3230 may provide power of the SSD 3200 when power supplyfrom the host 3100 is not smooth. For example, the auxiliary powersupply 3230 may be positioned in the SSD 3200 or may be positionedoutside the SSD 3200. For example, the auxiliary power supply 3230 maybe positioned on a main board and may provide auxiliary power to the SSD3200.

The buffer memory 3240 operates as a buffer memory of the SSD 3200. Forexample, the buffer memory 3240 may temporarily store data received fromthe host 3100 or data received from the plurality of flash memories 3221to 322 n or may temporarily store meta data (example e.g., a mappingtable) of the flash memories 3221 to 322 n. The buffer memory 3240 mayinclude a volatile memory such as a DRAM, an SDRAM, a DDR SDRAM, anLPDDR SDRAM, and a GRAM, or a non-volatile memory such as an FRAM, aReRAM, an STT-MRAM, and a PRAM.

FIG. 14 illustrates a user system to which the storage device accordingto an embodiment of the present disclosure is applied.

Referring to FIG. 14, the user system 4000 includes an applicationprocessor 4100, a memory module 4200, a network module 4300, a storagemodule 4400, and a user interface 4500.

The application processor 4100 may drive components, an operating system(OS), a user program, or the like included in the user system 4000. Forexample, the application processor 4100 may include controllers,interfaces, graphics engines, and so on, which control the componentsincluded in the user system 4000. The application processor 4100 may beprovided as a system-on-chip (SoC).

The memory module 4200 may operate as a main memory, an operationmemory, a buffer memory, or a cache memory of the user system 4000. Thememory module 4200 may include a volatile random access memory such as aDRAM, an SDRAM, a DDR SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, an LPDDR SDARM,an LPDDR2 SDRAM, and an LPDDR3 SDRAM, or a non-volatile random accessmemory, such as a PRAM, a ReRAM, an MRAM, and an FRAM. For example, theapplication processor 4100 and memory module 4200 may be packaged basedon a package on package (POP) and provided as one semiconductor package.

The network module 4300 may communicate with external devices. Forexample, the network module 4300 may support wireless communication suchas code division multiple access (CDMA), global system for mobilecommunications (GSM), wideband CDMA (WCDMA), CDMA-2000, time divisionmultiple access (TDMA), long term evolution, Wimax, WLAN, UWB,Bluetooth, and Wi-Fi. For example, the network module 4300 may beincluded in the application processor 4100.

The storage module 4400 may store data. For example, the storage module4400 may store data received from the application processor 4100.Alternatively, the storage module 4400 may transmit data stored in thestorage module 4400 to the application processor 4100. For example, thestorage module 4400 may be implemented as a non-volatile semiconductormemory element such as a phase-change RAM (PRAM), a magnetic RAM (MRAM),a resistive RAM (RRAM), a NAND flash, a NOR flash, and athree-dimensional NAND flash. For example, the storage module 4400 maybe provided as a removable storage device (removable drive), such as amemory card, and an external drive of the user system 4000.

For example, the storage module 4400 may include a plurality ofnon-volatile memory devices, and the plurality of non-volatile memorydevices may operate identically to the memory device 100 described withreference to FIG. 1. The storage module 4400 may operate identically tothe storage device 50 described with reference to FIG. 1.

The user interface 4500 may include interfaces for inputting data or aninstruction to the application processor 4100 or for outputting data toan external device. For example, the user interface 4500 may includeuser input interfaces such as a keyboard, a keypad, a button, a touchpanel, a touch screen, a touch pad, a touch ball, a camera, amicrophone, a gyroscope sensor, a vibration sensor, and a piezoelectricelement. The user interface 4500 may include user output interfaces suchas a liquid crystal display (LCD), an organic light emitting diode(OLED) display device, an active matrix OLED (AMOLED) display device, anLED, a speaker, and a monitor.

What is claimed is:
 1. A volatile memory controller that controls avolatile memory device, the volatile memory controller comprising: anerror correction circuit configured to: receive write transactions froman external host, wherein the write transactions store data in thevolatile memory device; and generate codewords used when performingerror correction encoding on data corresponding to the writetransactions; and a data aggregator configured to: generate a mergedtransaction in which write transactions that correspond to a burstlength of the volatile memory device are merged; and provide the mergedtransaction to the volatile memory device by performing a burstoperation, wherein the burst operation is an operation of storing datawhile sequentially decreasing or increasing an address of any one of thewrite transactions included in the merged transaction.
 2. The volatilememory controller of claim 1, wherein the data aggregator comprises: ascheduler configured to store the write transactions; an internal bufferconfigured to store codewords corresponding to the write transactions;and an aggregation controller configured to generate the mergedtransaction according to whether the write transactions corresponding tothe burst length are stored in the scheduler.
 3. The volatile memorycontroller of claim 2, wherein the aggregation controller provides awrite completion response to the error correction circuit in response tothe codewords received from the error correction circuit, wherein thewrite completion response indicates the write transactions are complete.4. The volatile memory controller of claim 2, wherein the aggregationcontroller controls the volatile memory device to perform a flushoperation of providing each of the write transactions stored in thescheduler to the volatile memory in response to an event signalgenerated in the volatile memory.
 5. The volatile memory controller ofclaim 2, wherein, when an address of a write transaction input to thescheduler is not continuous with an address of write transactions storedin the scheduler, the aggregation controller controls the volatilememory device to perform a flush operation of providing each of thewrite transactions stored in the scheduler to the volatile memory. 6.The volatile memory controller of claim 2, wherein, when a readtransaction having a same address as an address of one of the writetransactions stored in the scheduler is received, the aggregationcontroller controls the volatile memory device to perform a flushoperation of providing each of the write transactions stored in thescheduler to the volatile memory.
 7. The volatile memory controller ofclaim 2, wherein, when a forced flush request is received from theexternal host, the aggregation controller controls the volatile memorydevice to perform a flush operation of providing each of the writetransactions stored in the scheduler to the volatile memory.
 8. Thevolatile memory controller of claim 1, wherein addresses of writetransactions included in the merged transaction are continuousaddresses.
 9. The volatile memory controller of claim 1, wherein theburst length corresponds to the number of sequentially decreasing orincreasing the address of any one of the write transactions.
 10. Astorage device, comprising: a nonvolatile memory device; a main memoryconfigured to temporarily store data related to controlling thenonvolatile memory device; and a memory controller configured to controlthe nonvolatile memory device and the main memory under control of anexternal host, wherein the main memory generates a merged transaction byaggregating a number of write transactions having continuous addresses,among write transactions received from the memory controller, equal to aburst length unit of the main memory, and processes the mergedtransaction via a burst operation, and wherein the burst operation is anoperation of storing data while sequentially decreasing or increasing anaddress of any one of the write transactions included in the mergedtransaction.
 11. The storage device of claim 10, wherein the main memorycomprises: an error correction circuit configured to generate codewordsassociated with performing error correction encoding on datacorresponding to write transactions included in the merged transaction;a data aggregator configured to provide a write complete response basedon the generation of the codewords; and a main memory device configuredto store the codewords.
 12. The storage device of claim 11, wherein thedata aggregator: generates the merged transaction in which writetransactions corresponding to the burst length unit are merged; andprovides the merged transaction to the main memory device via a burstoperation.
 13. The storage device of claim 12, wherein addresses ofwrite transactions included in the merged transaction are continuousaddresses.
 14. The storage device of claim 10, wherein the burst lengthcorresponds to a number of sequentially decreasing or increasing theaddress of any one of the write transactions.
 15. The storage device ofclaim 10, wherein, when a write transaction having a discontinuousaddress from addresses corresponding to the write transaction isreceived, the main memory processes each of the write transactions. 16.The storage device of claim 10, wherein, when a forced flush request isreceived from the memory controller, the main memory processes each ofthe write transactions.
 17. The storage device of claim 16, wherein,when a sleep mode for reducing power consumption of the storage deviceor a sudden power off occurs, the memory controller provides the forcedflush request to the main memory.